1. Field of the Invention
The present invention relates generally to fabrication processes for transistors. More particularly, it relates to a process for fabricating ultra-low contact resistances in GaN (Gallium Nitride)-based heterojunction field-effect transistors (HFETs).
2. Description of the Related Art
Recent rapid progress in GaN HFET technology provides convincing evidence that this technology will ultimately have a big impact on a wide range of systems, including future generation radar and satellite communications systems. See, for example, U.S. Pat. No. 6,100,548 relating to modulation-doped field-effect transistors and fabrication processes and U.S. Pat. No. 5,766,695 relating to a method for reducing surface layer defects in semiconductor materials having a volatile species.
FIG. 1 shows a cross section of a conventional GaN-based HFET structure, indicated with 1. This structure includes a first semiconductor layer 2 which has a first band gap and is doped with a charge carrier (e.g., an N-type dopant in the form of silicon). Usually this layer 2 is Al0.15Ga0.85N and is approximately 200 angstroms thick. This layer is a donor layer and is doped to have an electron density in the range of 1-2×1018 cm−3. The structure 1 also includes an undoped second semiconductor layer 3 positioned below the first semiconductor layer 2. The second semiconductor layer 3 has a second band gap that is less than the first band gap. This second layer is undoped GaN with a thickness of about 2 micrometers and generates a two-dimensional electron gas 4 in the semiconductor structure 1. A third semiconductor layer 5 is positioned between the first and second semiconductor layers 2 and 3. This “spacer” layer 5 is undoped. Although it decreases the carrier density in the two-dimensional electron gas 4, it further enhances the carrier mobility. The spacer layer 5 is Al0.15Ga0.85N and is about 30 angstroms thick.
A source ohmic contact 6 and a drain ohmic contact 7 are formed on top of the structure 1. The ohmic contacts 6, 7 are generally fabricated by evaporating a metal system of titanium, aluminum, nickel and gold (Ti/Al/Ni/Au) onto the layered semiconductor structure 1. The preferred ratios for those elements are Ti=6%, Al=65%, Ni=13%, and Au=16%. This metal system is then alloyed at an elevated temperature (e.g., 900° C.) so that it penetrates the layered semiconductor structure 1 (as indicated by broken lines 8) and communicates with the two-dimensional electron gas 4.
The breakdown voltage (from drain to source) of the HFET structure would be degraded if the ohmic contacts 6, 7 directly contacted the highly doped first semiconductor layer 2. Accordingly, a cap layer 9 is usually carried over the first semiconductor layer 2 and the ohmic metal system of these contacts is evaporated on this cap layer. The cap layer is Al0.15Ga0.85N and has usually the lightest doping that can be fabricated. This doping level is typically referred to as an unintentional doping (UID) level because some doping will inevitably be present.
An e-beam resist 10 is also formed over the layered semiconductor structure 1. A gate pattern is written into the resist 10 with an e-beam and, subsequently, a metallic gate 11 is evaporated into the gate pattern. The first and second semiconductor layers 2 and 3, the spacer layer 5, the ohmic contacts 6 and 7 and the cap layer 9 are carried on an insulating substrate 12, for example sapphire with a thickness of about 250 micrometers.
The fabrication process of GaN devices is a fundamental step for the viability of GaN device technology. In particular, the ability to make low and reproducible ohmic contacts to the channel of the GaN device is of utmost importance. Low ohmic contact resistance is crucial for high-performance devices. Lower contact resistance results in higher speed and gain for the device. Resistive heating is also reduced, therefore increasing reliability and efficiency. High efficiency is a key requirement for power devices. Reproducibility of the contact resistances is also a critical requirement for manufacturability, particularly for MMIC (monolithic microwave integrated circuit) fabrication.
In the GaN HFET structure above described, the ohmic contacts 6, 7 are created by depositing a metalization stack on the surface of the semiconductor, and by subsequently applying an annealing process to alloy the metal with the semiconductor. This approach works very well for GaAs and InP-based materials and devices. However, for GaN-based materials, this approach yields high contact resistances because the presence of the wide band-gap barrier layer, AlGaN, inhibits the ohmic metals from diffusing into the channel and forming proper contacts. Conventional alloy contacts in GaN-based HFET devices usually result in a contact resistance of 2.0 Ω/mm. This contact resistance is ten times the value of contact resistances of GaAs-based devices.